In the semiconductor industry, there is a need to enable differentiation between single chips for purposes, for example, of: manufacturing control; tracking of the chips' history; and identification and serial numbers in various applications.
The semiconductor manufacturing processes for mass production in general is based upon methods for making a large number of “many-of-the-same” chips, and therefore, to differentiate between chips effectively and efficiently without compromising the manufacturing throughput capacity, cost and quality is a major challenge.
Depending on the purpose for the differentiation and on the abilities of the available technology, various solutions have been presented in the prior art.
For manufacturing control and chip history tracking, visual identification solutions have been proposed. Examples include the following:
U.S. Pat. No. 6,063,685 to Steffan et al., which describes a method for visual identification by inscribing characters on a chip with laser direct write;
U.S. Pat. No. 4,510,673 to Shils et al., which describes visible human and machine-readable laser scribed identification; and
U.S. Pat. No. 5,350,715 to Lee, which describes a visual dot matrix for chip-on-wafer location data.
Software solutions of various kinds have been proposed to implement ID or serial numbers in microprocessors and other chips. These may comprise numbers being programmed and stored in non-volatile memories (NVM) of various types and used by the processor through memory reads, typically via a bus.
U.S. Pat. No. 6,018,686 to Orso et al. describes an IC with manufacturing information stored in non-volatile memory.
U.S. Pat. No. 5,732,207 to Allen et al. describes a microprocessor with on-chip EPROM holding manufacturing and configuration information.
U.S. Pat. No. 5,774,544 to Lee et al. describes an apparatus and method for encrypted serial numbers for a CPU die stored in a non-volatile RAM die, both within a single package.
U.S. Pat. No. 5,790,663 to Lee et al. describes a software apparatus and method for access to an encrypted serial number.
U.S. Pat. No. 5,794,066 to Dreyer et al. describes an apparatus and method for identifying microprocessor data of origin, type, stepping, and other parameters, stored in constant ROM or regular registers
Various hardware solutions including fuses or anti-fuses have been proposed. Some of them are programmed with high voltage or current, and some are programmed with external means, like laser cutting or welding. The following are examples of the prior art:
U.S. Pat. No. 5,672,994 to Au et al., the disclosure of which is hereby incorporated herein by reference, describes an improved antifuse MOSFET;
U.S. Pat. No. 4,916,809 to Boudou et al. describes a method for programmable laser welding anti-fuses;
U.S. Pat. No. 4,937,475 to Rhodes et al. describes a programmable circuit where conductor links are broken or connected by laser; and
U.S. Pat. No. 6,065,113 to Shiell et al. describes a method including an identifier in a microprocessor implemented by means of an OTP register including laser breakable fuses, fuses or anti-fuses programmed by current, or an identifier stored in an EPROM or written by e-beam in an all e-beam lithography process.
In some cases, it is known in the art to combine optical parallel lithography with e-beam lithography. Examples of the prior art include:
U.S. Pat. No. 5,994,030 to Sugihara et al., which describes a lithographic system combining optical lithography with e-beam exposure for improved resolution and throughput;
Japan Public-disclosure No. 4-155812, assigned to Hitachi, which describes a method for combining optical lithography with e-beam through a phase-shift mask; and
Japan Public-disclosure No. 1-293616, assigned to NEC, which describes a method for manufacture of IC's using a common optical light exposure and then an e-beam for writing patterns specific to each IC.
The following patents and publications are examples of other prior art:
U.S. Pat. Nos. 5,357,077; 5,350,715; 4,510,673; 5,109,149; 5,937,270; 5,808,268; 481,102; 5,721,150; 5,727,231; 5,903,490; 5,903,490; 5,679,967; 5,619,062; 5,545,904; 5,111,273; 4,937,475; 4,931,671; 4,875,971; 5,607,801; 4,720,470; 4,720,470; 5,093,550; 5,410,124; and 5,733,711
Examples of other prior art are also found in the following publications:
1987 Japanese patent JP62194565A2 to Isao et al. for a microprocessor with an EPROM for writing security information in it.
IBM Technical Disclosure Bulletin (TDB) article from August 1987, pp. 1284-1285, which describes a security system for protection of data contained on a disk.
January 1988 article from Oki Technical Review 129 by Yoshida and Tanakawa on a one-chip microcomputer for IC cards with a secure EEPROM area.
The disclosures of the following U.S. provisional patent applications, describing aspects of the present invention and having identical inventorship with the present invention, are hereby incorporated herein by reference:
U.S. patent application Ser. No. 60/177,087, filed Jan. 20, 2000;
U.S. patent application Ser. No. 60/189,756, filed Mar. 16, 2000; and
U.S. patent application Ser. No. 60/191,208, filed Mar. 22, 2000.
The disclosures of all references mentioned above and throughout the present specification are hereby incorporated herein by reference.